The present invention relates to a circuit technology, and more specifically, relates to a clock signal controller.
The quality of a clock signal determines the performance of an integrated circuit to a great extent. In a traditional design, a clock tree technology is employed to provide a clock signal. In the clock tree, an original clock signal is outputted from a clock source. Theoretically speaking, the clock signal may be directly provided to all elements using the clock signal, e.g., a register or a latch. However, actually, since the clock path is too long, the driving capability of the clock signal will be weakened. At this point, it needs addition of an inverter or buffer on the clock path, so as to enhance the driving capability of the clock signal. It would be appreciated that the driving capability of the enhanced clock signal might be weakened again, such that it needs re-addition of an inverter or buffer. From the perspective of the entire clock path, these added inverters or buffers form nodes in the tree structure.
Those skilled in the art would appreciate that propagation of the clock signal on the clock path has a delay. As aforementioned, on the clock path from the clock source to an element using the clock signal, there comprise a plurality of inverters or buffers. These inverters or buffers are one of important factors that cause the delay. The delay caused by inverters or buffers has a great uncertainty due to many factors such as the manufacturing process of the inverters or buffers, the operating temperature, the power source noise, and the like. Such uncertain delay greatly affects the performance of the integrated circuit. For example, for two elements adjacent on a data path, their clock signals may come from different clock paths; if the two clock signals are large-skew seriously, they cannot cooperate with each other. With the increasingly higher chip work frequency (i.e., the clock signal frequency), such adverse impact becomes more and more significant.
In order to overcome the above problem, a clock mesh technology is developed. The clock mesh technology realizes synchronization of the clock signals within a certain range of the chip. Specifically, with the clock mesh technology, a mesh structure may be formed within the range, and the clock signal on each point of this structure may be regarded as being small-skew. Correspondingly, each element within the range obtains nearby a clock signal from the mesh structure, such that these elements are driven by the small-skew clock signals.
For a large integrated circuit with complex functions, the clock mesh can only be realized at a local part of the chip from the perspective of power consumption and wiring. Besides, the clock mesh technology can only achieve a sound performance usually in the case that the range is of a regular shape. However, in many cases, a chip always includes many clock domains, and these clock domains do not have a regular shape. Therefore, it is hard to establish a corresponding clock mesh for these clock domains.
Hence, a new solution is desired to handle the issue of large-skew clock signals.